1. Field of the Invention
The present invention generally relates to a method of fabricating dynamic random access memory (DRAM) cells, and more particularly, to producing a DRAM cell having lower strap resistance, fewer surface strap shorts and reduced wordline capacitance.
2. Background Description
Current DRAM technologies have many problems. First, high strap resistance occurs at low temperatures. It is believed that the temperature sensitivity of the strap is due to interface resistance resulting from native interfacial oxide. Second, there is a high incidence of gate conductor to surface strap shorts. Two Reactive Ion Etches (RIE) of the spacer nitride are required during strap formation, one for removal of a borophosphorous silicate glass (BPSG) layer and one for Trench Top etch. Third, many known processes are undesirably complex for manufacturing purposes.
A conventional process opens a window in the BPSG prior to deposition of strap polysilicon. This requires that the interface be clean to assure a low resistance contact between strap and polysilicon node and between the strap and the active area. However, the effects of native oxide and other contaminants on the exposed surfaces frequently result in poor strap resistance at low temperature.